Ams Verification Engineer

We are seeking an experienced Senior Analog Mixed Signals Verification Engineer to join our team in the semiconductor industry. The ideal candidate will have a strong background in analog and mixed-signal simulation, with hands-on experience in writing behavioral models, using simulation tools like SPICE, and performing verification using SystemVerilog (SV) and UVM (Universal Verification Methodology). You should be able to work effectively in a team environment and collaborate with cross-functional teams to ensure high-quality verification for complex analog and mixed-signal designs.

Key Responsibilities:

• Mixed Analog and Digital Simulation: Perform verification of analog and mixed-signal designs using industry-standard simulation tools. Ensure the simulation models and tests cover all necessary use cases.
• Behavioral Modeling: Write and develop behavioral models for analog blocks, enabling effective simulation of analog and mixed-signal systems.
• Analog Modeling with SPICE: Use SPICE-based tools for simulating analog blocks, ensuring accuracy and performance for design validation.
• Simulation Using Digital Logic: Leverage behavioral models and integrate digital logic into analog simulations to create a comprehensive mixed-signal environment.
• SV/UVM-based Verification: Lead and execute verification of mixed-signal designs using SystemVerilog (SV) and UVM methodology, ensuring robust, reusable, and scalable testbenches.
• Team Collaboration: Work closely with other engineers in a collaborative environment to integrate and verify complex analog/digital mixed-signal designs, ensuring smooth communication and effective workflow.
• Issue Resolution: Identify, debug, and resolve verification issues and provide technical feedback to design teams to improve the designs.
• Documentation: Maintain thorough documentation of verification plans, testbenches, and results. Prepare reports on verification status and findings for management and stakeholders.

Desired Profile of the Candidate:

• Experience: A minimum of 4 years of experience in analog and mixed-signal verification within the semiconductor industry. Up to 10 years of experience is preferred.
• Behavioral Modeling Expertise: Strong experience in writing behavioral models for analog blocks and using them in simulations for verification.
• Analog Simulation Proficiency: Proficient in simulating analog models using tools such as SPICE and other similar platforms.
• Mixed-Signal Verification: In-depth knowledge of mixed-signal verification, particularly using digital logic in conjunction with analog models.
• SV/UVM Knowledge: Solid experience in using SystemVerilog (SV) and UVM for verification, including creating and running testbenches, debugging, and ensuring functional correctness.
• Communication Skills: Strong written and verbal communication skills to effectively report verification results, interact with design teams, and document findings.
• Team Player: Ability to work well within a team and collaborate with other teams (design, validation, and other cross-functional groups) to achieve project goals.
• Problem-Solving: Strong problem-solving skills, particularly in debugging complex verification issues and identifying root causes in mixed-signal environments.

Required Skills & Qualifications:

• Technical Skills:
• Mixed Analog-Digital Simulation: Experience with both analog and digital simulation tools (SPICE, SystemVerilog, UVM, etc.).
• Analog Behavioral Modeling: Experience in creating and using behavioral models for analog circuits.
• Verification Methodologies: Solid experience in applying SV/UVM-based methodologies for verification.
• Tools and Languages: Familiarity with EDA tools (e.g., Cadence, Synopsys, Mentor Graphics), SPICE simulators, and other verification tools.
• Education: Degree in Electronics, Electrical Engineering, or a related field (Masters or Bachelors).