Technology Enablement Engineer

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.

Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies.

This role is based in Noida. But you ll also get to visit other locations in India and globe, so you ll need to go where this job takes you. In return, you ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come.

• Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes.
• Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing.
• Are you expertized in working through complex technical issues and independently building solutions and new methodologies!
• Explain complex principles in simple terms to broad audiences.
• Some travel, domestic and international.
• Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs.
• Working closely with our key customers on deployment challenges.
• Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings.
• Architecture reviews of customer designs.
• Closely working with AEs to gather top issues blocking their engagements success.
• Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U.

• BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 2-5 years of experience.
• Knowledge of design logic design languages, tool usage, design flow steps required.
• We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs.
• ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation.
• Knowledge of a scripting language like TCL.
• We need someone self-motivated and dedication to improvement with strong problem-solving skills.
• Excellent organizational skills, written and verbal English language communication skills.
• Proficiency in LINUX and Windows environments.

The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged.