As a verification engineer, you would be required to formulate and implement verification strategy for these highly configurable designs. The work would involve developing UVM based environments, RISC-V assembly programs or tools for improving the overall verification methodology. You will get a hands on exposure to the state of the art design and verification philosophies catering to different domains like embedded, high performance, AI or security.
Required Skill Set
Basic digital design, Computer Architecture is a must.
Good to have: Verilog design exposure, RISC-V Assembly, Python, UVM/CoCoTb for verification.