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Senior Engineer I - VLSI
Open Silicon Research
posted 3mon ago
Job Role Insights
Flexible timing
Key skills for the job
Job Description
The Opportunity
Were looking for the Wavemakers of tomorrow.
What Youll Do:
- Complex high-speed designs for edge computing applications (3.2G HBM PHY, Processor hardening for PPA analysis)
- work on Functional DFT modes and constraints, Signal integrity, knowledge of de-rates (OCV, AOCV,POCV)
- Will need to be hands-on, defining constraints, margins based on tech nodes, incorporating feedback from the Analog Team in the SDCs
- 5 years of experience with EDA Tools and Methodologies for STA, STA-based ECO, Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating
- Correlate results between STA and GLS with AMS
- power management and UPF concepts at Synthesis/PnR/STA domains
- you will be reporting to Director - IP Design.
What Youll Need:
- Experience in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....)
- Experience in Timing Closure/ECOs on block level and chip level in a highly complex clocking environment including clear understand of clock domain crossings, Should be able to work closely with Physical Design Teams
- Good scripting skills; experience in Tempus is a plus
- Experience in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....)
- Experience in Timing Closure/ECOs on block level and chip level in a highly complex clocking environments including clear understand of clock domain crossings, Should be able to work closely with Physical Design Teams
- Good knowledge of Functional DFT modes and constraints, Signal integrity, Good knowledge of de-rates (OCV, AOCV,POCV)
- Will need to be hands-on, defining constraints, margins based on tech nodes, incorporating feedback from the Analog Team in the SDCs
- should have worked with EDA Tools and Methodologies for STA, STA-based ECO, Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating
- Correlating results between STA and GLS with AMS
- Understanding of power management and UPF concepts at Synthesis/PnR/STA domains
Hybrid work environment
As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:
- Competitive Compensation Package
- Restricted Stock Units (RSUs)
- Hybrid Working Model
- Provisions to pursue advanced education from Premium Institute, eLearning content providers
- Medical Insurance and a cohort of Wellness Benefits
- Educational Assistance
- Advance Loan Assistance
- Office lunch Snacks Facility
Diversity Inclusivity
Accommodation
Alphawave Semi is an equal opportunity employer and welcomes applications from all qualified individuals, including visible minorities, Indigenous People, and persons with disabilities. We welcome and encourage applications from people with disabilities. If as a qualified job applicant, you request accommodation, Alphawave Semi will consult with you to provide reasonable accommodations according to your specific needs. If you wish to make a request, you will be provided an opportunity if you re applications is selected to proceed in our hiring process.
Employment Type: Full Time, Permanent
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What Senior Engineer at Open Silicon Research are saying
Senior Engineer salary at Open Silicon Research
reported by
4
employees
with 4-8
years exp.
₹12.8
L/yr - ₹39.3
L/yr
147%
more
than the average Senior Engineer Salary in India
View more details
What Open Silicon Research employees are saying about work life
based on 4 employees
Flexible timing
Monday to Friday
No travel
Open Silicon Research Benefits
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