ICB3-Senior Design Engineer

Broadcom Central Engineering team is looking for a Mutiskilled PNR, STA, RTL /DFT Engineer. The Successful candidate will work in one or more domains of RTL, Verification, PNR, DFT and STA for Complex Memory, IO subsystems, ARM processor Blocks including BIST. It is great Opportunity and challenging role for the people who wants to gain in depth knowledge on end to end Chip development flow from RTL to GDS2 with Deeper Expertise in DFT and Memory BIST.

Memory/IO Subsystem RTL, DFT, PNR/STA Designer

RTL development and Verification for Digital, Memory Subsystems including BIST. DFT Insertion and Verification signoff for IO, ARM-PNR, Memory Digital Subsystems with Tessent/Embedded MBIST RTL to GDS2 flow development in 5FF, and below technology for the Automation for Complex Digital subsystems. MBIST, ATPG, RSQ Verification and sign-off. Static timing analysis, formal verification, Cross Clock Domain checks, Power/Timing sign off Verify complex Subsystems through OVM, UVM methodology, creating the Verification Suit Independently. Define the Floor Plan/placement/routing/Timing constraints in ICC for Complex blocks including Memory BIST to achieve correct by construct DRC/LVS and timing closure Define and standardize STA recipe by interacting with BUs/Central Recipe team to drive Seamless timing closure for broader subsystems. Interact with the Cross functional IP teams, Flow teams, (Synthesis/STA/DNE) to close the loop in timing violations/DRC/LVS. ICC/Synthesis/STA constraints automation to achieve predictable timing closure correct by construct DRC/LVS through automation with minimal randomness.