Senior Engineer - Design Verification

Quest Global is an organization at the forefront of innovation and one of the world\u00E2\u20AC\u2122s fastest growing engineering services firms with deep domain knowledge and recognized expertise in the top OEMs across seven industries. We are a twenty-five-year-old company on a journey to becoming a centenary one, driven by aspiration, hunger and humility.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible, possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers.

As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we\u00E2\u20AC\u2122re eager to hear from you.

The achievers and courageous challenge-crushers we seek, have the following characteristics and skills:
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• Knowledge of Code coverage using features in existing simulators or stand-alone tools like Surecov, HDL score etc.
• Working on full chip verification and OVM/UVM Methodology, System Verilog is a must with 3+years of recent work experience, worked on passing test cases, test benches, Building environment.
• Knowledge of Functional coverage using HVL language features or assertions a plus.
• Should be ARM based SoC verification only. No need to mention tools.
• Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc.

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Desired Skills & Experience:

• Experience level 3 to 8 years.
• Strong domain knowledge on one or more - PCIe,USB, Ethernet, ARM, AHB/AXI, AMBA, Networking, CPU, ARM, Graphics (DDR, PCIE, USB)
• Should have worked on SOC verification on at least one project with constrained random methodology (OVM/UVM).
• Good in concepts Code coverage and functional coverage.
• Expertise in Verilog and / or VHDL is desired.
• Strong in SV & OOPS
• IP or SoC verification
• Functional + code coverage
• ARM based SoC verification
• Capable of developing C tests
• Working knowledge \u00E2\u20ACSV/METH
• Code coverage

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