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Lead MTS Layout Design
Rambus
posted 3mon ago
Job Role Insights
Flexible timing
Key skills for the job
Job Description
- Should lead a team of 6 to 8 members and will be responsible for execution of the assigned project/program.
- Responsible for providing technical guidance to the team and coordinating with project functional groups (Design, PNR, CAD, Foundry etc.) for layout deliverables.
- Should have strong collaboration with Analog Designers across the globe to solve challenging problems.
- Working on layout design of owned blocks with Cadence Virtuoso XL.
- Working on block and top-level/sub-hierarchy level layout verification with Calibre.
- Extensive Top/Chip level layout experience
- Familiarity with various Tape out procedures, Physical verification for tape out (LVS, DRC, Density, Extraction, EM).
- Expertise in standard layout practices such as Layout matching, parasitic, noise noise isolation, supply consideration, latch up, shielding, Well s substrates and Isolation.
- Strong fundamental knowledge in semiconductor device physics, cross-section, and construction
- Strong fundamental knowledge in layout principles, IC reliability, and failure mechanisms
- B.Tech/BE with 10 to 14 years of relevant layout experience.
- Should have experience in doing layouts for process nodes from 40nm, 28nm, 22nm, FINFET nodes (16nm, 12nm, 7nm).
- Should have exposure to chip level floor plan, power grid, good understanding of EM/IR at chip level.
- Sound knowledge of pad placements, ESD/Latchup requirements.
- Sound knowledge of device matching, double pattering and other layout dependent effects. Knowledge of scripting on SKILL, PERL is an added advantage.
- Familiarity with package selection procedures and design checks.
- Good team player with self-motivation and excellent communication skills.
Employment Type: Full Time, Permanent
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based on 3 employees
Flexible timing
Monday to Friday
No travel
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