PE Verification Engineering

Duties in this position will include:

Testbench and test sequence development for verification of new controller technologies and features

Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage

Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design

Development & support of Verification environment scripting and capabilities

Bachelors Degree or above in EE/CS, minimum 10-15 years experience with HDL logic Design-Verification

System Verilog / UVM testbench, Verilog/System Verilog logic design/RTL fluency a must

Pre-existing Experience / familiarity with PCI-Express controller and protocol required

Working experience with Python and TCL scripting languages preferred