Senior DFT Engineer

Looking for DFT lead who can drive a 10 member DFT team. Candidate should have hands on experience on SSN, MBIST, LBIST, Scan Insertion, ATPG, GLS and post silicon debug

Should be able to handle large scale SOC for hierarchical scan insertion and SSN based ATPG flow.
Integration and Verification of MBIST at RTL level.
RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST.
Implementation and Verification of IEEE1149.1 JTAG, IJTAG standards.
Post silicon debug activities for DFT patterns.
Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role.

BTech/MTech degree in Electronics/Electrincal engineering

7+ years of experience in DFT domain

Expert on EDA tools such Tessent, Genus, FC, VCS and Conformal/Formality etc

Knowledge on SSN based architecture

Good scripting skills ( PERL/TCL/Python)

Good communication skill

Should be able to mentor junior DFT engineers