Staff ASIC Design Engineer

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Skills & Experience

MTech/BTech in EE/CS with 7-12 years of ASIC Design experience.

Strong fundamentals and experience in micro-architecture development and RTL Digital design

Exposure to front-end flows (Lint, CDC, low-power checks, Synth etc.)

Domian knowledge in LP/PC DDR 2/3/4/5 highly desirable

Understanding of protocols like AXI/ACE/CHI/AHB is highly desirable

Must possess good communication skills; prior experience working with global teams is desirable

Experience with post-silicon bring-up and debug is a plus

Lead/guide junior engineers to deliver multiple IPs with good quality and on schedule

Must be flexible to contribute in various capacities (beyond RTL design) to the end product goals

Responsibilities

Mirco architecture & RTL development in consultation with Architecture and Systems teams

RTL Front-end quality checks

Work with functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels.

Hands on experience in constraint development and timing closure.

PPA efficient design and low power checks

Support performance debugs and address performance bottlenecks

Provide support to sub-system, SoC integration and chip level debug.

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