Turing Design Verification - Sr Lead Engineer

Being part of this team will give you exposure to the design and verification of latest Qualcomm AI/ML/DL IP's/Core

Being a part of the DV Team, you will work on Functional , Formal Power aware and Gate level simulation

Get to work on the latest and cutting-edge tech nodes

Required to work on IP verification and own various DV tasks from Test plan creation, coverage model development, test case writing and coverage closure.

• Should be proficient in System-Verilog and scripting language like Shell, Perl . Must have RTL/gate level simulation debug experience.
• Should have a working knowledge of bus protocols like AHB/AXI .
• Candidates should have 5-8 years experience.
• Good in SV, UVM, Assertions, GLS
• Solid knowledge of C and Scipting language like python
• Working knowledge of bus protocol like AHB/AXI