ASIC Design Verification Engineer

Job Title: ASIC/RTL Verification Engineer (Junior to Lead)

Location: [Insert Location]
Experience: 412 years (Junior, Mid-level, Lead roles)
Employment Type: Full-time

About Us:

Join our team of innovators at ACL Digital, a leader in cutting-edge semiconductor solutions. We specialize in designing and delivering high-performance IPs, SoCs, and subsystems for a variety of applications, including AI, networking, storage, and consumer electronics. Be part of a dynamic environment where your expertise drives tomorrows technology!

Role Overview:

We are seeking highly motivated ASIC/RTL Verification Engineers to join our team and contribute to the verification of complex and high-speed IPs, SoCs, and subsystems. This role spans various methodologies, including functional, formal, CPU, and gate-level simulations (GLS). Youll work on advanced protocols such as PCIe, USB, Ethernet, DDR, and more, driving quality and performance across the design lifecycle.

Key Responsibilities:

• Develop and execute functional verification plans for IPs, SoCs, and subsystems.
• Perform formal verification to ensure design correctness and identify corner-case issues.
• Design and implement advanced testbenches using UVM/OVM/VMM methodologies.
• Conduct CPU verification and integrate processor cores into subsystems.
• Perform gate-level simulations (GLS) for timing and power analysis.
• Work on high-speed and complex protocols (e.g., PCIe, USB, DDR, Ethernet, MIPI).
• Debug simulation failures, identify root causes, and ensure first-pass success.
• Collaborate closely with design, architecture, and software teams to meet verification goals.
• Lead and mentor junior team members in best practices and advanced methodologies (Lead role).

Qualifications:

For Junior Engineers:

• Bachelors/Master’s degree in Electronics, Electrical, or Computer Engineering.
• 3–4 years of hands-on experience in ASIC/RTL verification.
• Familiarity with HDL (Verilog/VHDL) and scripting (Python/Perl/TCL).
• Basic knowledge of UVM/OVM methodologies and industry protocols.

For Mid-Level Engineers:

• 4–8 years of experience in functional and formal verification.
• Proficiency in developing and debugging testbenches using SystemVerilog/UVM.
• Experience with IP/SoC/subsystem verification and protocol compliance testing.
• Understanding of GLS and low-power verification techniques.

For Lead Engineers:

• 8–12 years of experience in ASIC/RTL verification.
• Expertise in verification planning, resource estimation, and execution.
• Strong leadership and mentoring skills.
• Hands-on experience with CPU verification and integration into SoCs.
• Proven track record in delivering high-quality silicon products.

Why Join Us?

• Opportunity to work on state-of-the-art technologies and high-speed protocols.
• A collaborative and inclusive culture focused on innovation and growth.
• Competitive compensation and benefits tailored to your experience.
• Career development opportunities, from hands-on learning to leadership growth.
• Be a part of a team that delivers industry-leading solutions impacting millions worldwide.

How to Apply:

Submit your resume to prabhu.p@acldigital.com or apply through our website: ACL Digital Semiconductor Careers. Let’s shape the future of semiconductors together!