CPU Synthesis CAD Engineer

 
Company: Qualcomm India Private Limited
 
Job Area: Engineering Group, Engineering Group > Hardware Engineering
General Summary:
NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.
Minimum Qualifications:
"¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
As CPU Synthesis CAD engineer, you will build and support the world"™s best front-end implementation tools and flows. Your tools and flows will ensure our custom Oryon CPUs have industry-leading power, performance and area.
Roles and Responsibilities

Develop, integrate and release new features in our high-performance synthesis CAD flow

Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area (PPA)

Maintain, support and debug front-end implementation flows, and resolve project-specific issues

Work closely with CPU Physical Design CAD engineers to result in tight vertical integration between front-end and back-end PPA.

Work closely with worldwide CPU synthesis/physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA.

Work with EDA vendors to define roadmap and to resolve tool issues

Preferred Qualifications:

Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science

10+ years of hands-on experience in synthesis/place-and-route of high-performance chips - either in a design or CAD role

High level of proficiency in Tcl as well as Python

Experience with automation

Experience with a wide variety of front-end tasks - logic synthesis, logic equivalency checking, low-power-intent (UPF), front-end signoff.

Solid understanding of digital design, timing analysis and low-power design

Solid understanding of RTL description languages such as Verilog and System Verilog.

Experience with advanced technology nodes (5nm or lower)

Strong user of industry-standard synthesis tools such as Cadence Genus or Synopsys Fusion Compiler, and front-end signoff tools such as Cadence LEC and Cadence Conformal Low Power

Proven track record of managing and regressing synthesis flows

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