PMIC Design Verification Engineer - Staff

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Digital Verification Engineer for IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions.

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create job s, and enrich lives.

But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in.



Digital Verification Engineer for for Mixed-Signals IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. IPs include telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G power (mmW, envelope tracking, high performance low noise oscillators etcâ"¦) and high efficiency power management (DC-DC charge pumps, bucks and linear regulators).

* Work includes partnering with international teams in all stages of development from system definition to high-volume (100M+) OEM launches.

* Digital Verification aspects include all stages of the verification process from test planning, UVM-compliant test-bench architecture, constrained-random stimulus creation, score-boarding and coverage closure.

* Work includes verification of digital and mixed-signals IPs and exposure to analog behavioral models is a plus.

* Work includes debugging of complex embedded systems including SOCs, firmware, embedded sequencers.

* Position includes IP or chip DV ownership including task planning and project risk mitigation.

* Work in a dynamic team environment with aggressive schedule towards metrics-based high quality target.



Preferred Qualifications

Strong troubleshooting skills across embedded systems disciplines (digital RTL, Firmware, analog behavioral models)

Strong communication and organizational skills

Strong process-oriented mindset.

Expert-level System Verilog Programming

Advanced UVM/SV (Universal Verification Methodology using System Verilog)

Python or Perl scripting



Minimum Qualifications

Bachelor's degree in Science, Engineering, or related field.

8+ years ASIC design, verification, or related work experience

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.


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