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Reliability Methodology and Validation Tech Lead
6-11 years
Bangalore / Bengaluru
Reliability Methodology and Validation Tech Lead
Intel
posted 3d ago
Job Role Insights
Job Description
- Define technical specification in the area of PERC ESD domain for Intel advance technology features to enable Intel-specific and industry standard EDA design tools.
- Coordinate development of these technology features, develop QA plans and drive test-cases development working with relevant stakeholders.
- Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification.
- Joint effort with partners in DE organization to evaluate and isolate performance contributors for technology features as part of enablement.
- Build and qualify Process Pathfinding Kits and tools with quick turnaround time.
- Drive innovation and initiatives to enhance existing automation, tools and methodology.
- Identify and analyse problems, plans, tasks and solutions.
- Cultivate and reinforce appropriate group values, norms and behaviours.
- Perform in a dynamic, challenging and sometimes ambiguous environment with drive and creativity
- The candidate should also exhibit the following behavioural traits and/or skills:Creative, independent, and out of the box thinker with strong problem-solving skills and analytical ability.
- Experience in driving cross-functional and industry wide initiatives and taskforces.
- Attention to details, strong organization skills
- Depth and Breadth being able to connect the dots and identify cross-discipline optimal solutions
- Self-motivated, strong leadership skills being able to influence across internal and external ecosystem\
- Written and verbal communication skills to present complex issues with clarity to drive decisions
- Able to work with cross-functional and cross site teams and influence multiple internal and external stakeholders
- Ability to work in a dynamic and team-oriented environment
- BS in EE/CE with minimum 10-year relevant industry experience OR MS in EE/CE with minimum 8 year relevant industry experience OR Ph.D. in EE/CE with minimum 6 year relevant industry experience in the following areas:
- Deep expertise in PERC ESD rule deck development in either Siemens Calibre or Cadence Pegasus or Synopsys ICV rule decks, new process node PDK enablement in PERC ESD space. This includes both Schematic front end design and in back end layout design side of implementation.
- Device level knowledge in ESD operational physics, expertise in modelling lower nm technology ESD complications and new challenging implementation and advancements.
- Expertise and multiple years of exposure in implementation or solving Schematic checks, LDL - p2p, CD checks in layout side.
- Planning, execution and validation of Strategic new initiatives in area of PERC ESD implementation, PDK rule decks and new EDA engagements.
- Parasitic Extraction, Device Modelling and Simulation tools/flows
- Custom design flow and related EDA tools
- CMOS device physics, process technology and design rules
- Tools, flows, and methodology for optimal Product Performance/Power/Area/Cost(PPA)one of the following: Python, PERL, TCL
- Preferred:Familiar with Reliability verification in lower nm nodes, ESD concepts, IO cell design and ESD execution.Familiarity with TVF, TCL and python automation in deep expertise extent.ICV python rule deck implementation expertise is preferred domain area.
Employment Type: Full Time, Permanent
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What people at Intel are saying
Rating based on 2 Technical Lead
reviews
Anonymous · Engineering - Hardware & Networks
in Bangalore / Bengaluru
Good work environment and very supporting team. We work on latest technology to give lot of motivation.
- Salary - Good
job security is very less. Adapting to the new changes in Chip design is less due to which we are loosing lot of market domination position. We are slow in adapting to AI revolution and stock value is down due to this.
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