Research Engineer/Senior Research Engineer - (QKC) CDOT

Job Role

Research Engineer/Senior Research Engineer (FPGA Design for QKD Related Applications)

No. of Vacancy

3

Location

Delhi

Qualification

• B.E./B.Tech. (ECE/CS/EE/EI/IT/VLSI) or M.Sc. (Physics) or M.E./M.Tech(ECE/CS/EE/EI/IT/VLSI/CE/Optical communication) with 60% / PhD (in relevant areas)

Experience

Minimum 2 years experience (industry/academic) (Not mandatory for candidates having a PhD)

Roles & Responsibilities

Skills

RTL coding and simulation in Verilog, VHDL or System Verilog.

Good coding skills in C, C++, python and shell script (bash).

Good knowledge of Xilinx /Intel-Altera FPGA architecture.

Exp. with FPGA synthesis tool- Xilinx Vivado, Altera Quartus Prime or similar, IP Core development, High-level synthesis design flow, Logic acceleration & optimization.

Experience in creating placement and timing constraints, synthesis, place and route, static timing analysis/FPGA timing closure and in-system debugging using ILA/SignalTap.

Good knowledge of FPGA processor subsystems, Linux operating system internals and Linux device driver development.

Knowledge of AMBA-AXI, PCI-E Gen 4, Ethernet, I2C, SPI, MII/MDIO interfaces.

Knowledge of TCP/IP Protocol Suite, Control Protocols such as DNS, DHCP, HTTP, HTTPS etc.

Knowledge of IP packet debugging tools such as Wireshark, tcpdump, ping, traceroute, nmap etc.

Good knowledge of Ethernet/IP packet capture, packet parsing & striping, packet de-duplication, payload compression & decompression, encryption & decryption etc. to be implemented using HDL for FPGA.

Experience with high-speed network interface (SFP/QSFP) design in FPGA.

Selected candidates will be responsible for working on FPGA hardware and development tools to accelerate various functions of an application using FPGA offloading.