Senior Engineer - Analog/Mixed Signal IP Integration

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

JR65718 Senior Engineer - Analog/Mixed Signal IP Integration

This position is for Analog Design Group located at Bangalore, India

*The seniority level offered will be based on a combination of experience and education.

What s Encouraged Daily:

Contribute to the development of new HBM products by assisting with the overall design and layout.

• Top-level implementation of Analog Blocks like LDOs, Charge Pumps, Oscillators, IOs, Buffers etc
• Establish IP Integration guidelines
• Understand load patterns for supplies and defining specs
• Interpret product specifications and design circuits to meet the required functionality
• Implement PDN integration and evaluation of IPs
• Take care of power-up sequence of multiple DRAM supplies, mitigating forward bias, stress and leakage risks
• Helping with top-level ERC, reliability and seamless integration of analog mixed signal IPs
• Develop flows to automate quality checks for deliverables IPs
• Propose measurable matrix to gauge success of clean integration
• Understand implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products.
• Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits.
• Parasitic modeling and design validation, reticle experiments and required tape-out revisions.
• Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.
• Mentor and lead young designers

Oversee the layout process

• Help floor-planning process, including placement and routing optimization
• Optimize design rules for cost, performance, and functionality
• Import layout parasitic information into the circuit simulation environment

Maintain Technical Expertise and Provide Training

• Contribute to cross-group communication to work towards standardization and group success
• Aid in design documentation and communicating best-known practices to the entire department
• Participate in continuing education and competitor analysis
• Proactively solicit feedback from Standards, CAD, modeling, and verification groups to ensure the design quality
• Drive innovation into the future Memory generations within a dynamic work environment

How To Qualify:

• BTech or Higher from reputed institute
• 2+ years of relevant Engineering experience working with analog/mixed signal IPs
• Extensive knowledge of CMOS circuit design, device physics, analog and mixed-signal circuit with experience in high-speed link, ESD
• Strong fundamental knowledge for AMS design, Advanced CMOS processes
• Understanding of Mismatch analysis & Monte-Carlo methodology/sims, transistor level Circuit level noise analysis. Understanding of device physics & deep-sub micron issues.
• Silicon delivery and debugging experience.
• Supervision of complex and/or sensitive analog layout and defining IP floorplan
• Experience with industry-standard tools such as Cadence ADE, Spectre, AMS verification, EM/IR flows, MATLAB, Calibre, etc.
• Excellent problem-solving and analytical skills
• A self-motivated, phenomenal teammate who enjoys working with others
• Good communication skills with the ability to convey complex technical concepts with peers in verbal and written form
• Experience with a scripting language (Python, Tcl, Perl, etc.)
• Experience with simulation and silicon validation of circuits