Staff Engineer HBM Verification

Develop and validate behavioral models for DRAM and related memory architectures.

Design and implement System Verilog UVM testbench and test cases.

Collaborate with circuit and architecture teams to understand custom circuits and translate them into high-level models.

Debug and resolve issues related to design, functionality, and performance in behavioral models.

Optimize behavioral models to ensure high simulation performance and accuracy.

Provide support for customer queries and model integration.

Required Skills (Must-Have). DRAM Block-Level Design Expertise Strong understanding of DRAM architecture, protocols, and functional blocks.

Verification Skills Proficiency in System Verilog and UVM for design verification.

Behavioral Modeling Experience Hands-on experience in developing and validating behavioral models for memory components.

Custom Circuit Debugging Ability to understand and debug custom circuit behavior.

Testcase Development Strong capability in creating and executing comprehensive test cases for validation.

Preferred Skills (Good-to-Have). Customer Support Experience in assisting customers with model integration and issue resolution.

Advanced Modeling Experience Exposure to modeling blocks like ECC (Error Correction Code), data aligners, JTAG, or IEEE 1500.

Team Collaboration Ability to work in cross-functional teams and provide technical guidance where required.

Scripting and Automation Knowledge of scripting languages (e.g., Python, Perl) for automation tasks is a plus.

Experience Required. Minimum 5+ years of hands-on experience in design and verification, with a focus on behavioral modeling and DRAM architecture.