Senior Manager/ Manager - Memory Circuit Design Verification

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

JR58233 Senior Manager/ Manager - Memory Circuit Design Verification

Description

As a Principal Memory Circuit Design Verification Engineer / Senior Manager / Manager, you will guide a highly innovative, motivated, young and dynamic design team capable of verifying complete products using state of the art memory technologies. You will need to have the ability to drive the team and the overall verification effort to ensure the timely delivery of a functionally correct design.

Unique Opportunities

• Complete ownership of verification and end to end analysis of complex full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4,LPDDR4,DDR5 and LPDDR5 that are capable of operating at high speeds of up to 6400MT/s.
• Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design.
• Work on cross functional tasks that can widen your skill set.

Responsibilities

• Guide and set the broader direction for the verification effort of any project that the team undertakes.
• Lead cross-site efforts in developing verification methodology and verification environments for advanced DRAM and emerging memory products.
• Provide advice to senior management on significant technical issues.
• Strive to establish best known methods within the group by driving development meetings, technical forums, etc.
• Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs.
• Develop Test cases/Stimulus to increase the verification coverage for all DRAM and emerging memory architectures and features.
• Drive development of test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.

Core Requirements

• Ability to drive and guide team for successful completion of the DRAM projects
• Analytical capability to analyze complex CMOS and gate level circuit designs
• Well versed with SPICE and Verilog simulations
• Good communication and leadership skills

Preferred Qualities

• Experience in SystemVerilog, PLI coding
• Experience in UVM Test Bench
• Experience in DRAM, SRAM or other memory related fields
• Experience in AMS verification and co-sim
• Considered expert in one or more verification domains

Education

Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required with 12 + yrs