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DFT Engineer
Meyvnsystems
posted 5d ago
Job Description
- Should have hands on experience in - DFT Architecture, Design, Scan, MBIST, Gate Level simulations with Timing, DFT Constraints, Pattern Generation and ATE support.
- Should be familiar with SoC & IP level DFT Architecuture and Flows from RTL till production.
- Able to understand and implement requirements from Test engineering perspective
- Familiarity with either Synoposys or Tessent Scan flows; Simulation tools: NCSIM/VCS
- Should have handled aspects of Scan Scan Insertion, ATPG, Coverage improvement, Pattern Generation on their own. Familiarity with various test pattern formats – STIL, WGL, VEC formats.
- Experienced in defining DFT constraints, Timing Closure in DFT modes and handling Gate level simulations with timing at various corners.
- Able to implement ECO flows to resolve issues observed at NETLIST level.
- Experienced in MBIST flows – Insertion, Simulation and Pattern generation.
- Ability to deal with Mixed-Signal design test controllability and observability can be a major plus.
- Should be able to support ATE and HTOL teams for Post-silicon debug support.
- Experience in Tcl/Tk, PERL, Makefile is a Plus
Employment Type: Full Time, Permanent
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Monday to Friday
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Day Shift
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