Senior Staff Engineer - DFT/DFX Verification

Custom Compute and Storage Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements in CCS BU.

• Create and execute test plans for functional and structural verification of DFT/DFX features in RTL and Gate-level Simulations.
• Candidate will be involved in DFX Test-development for validating a variety of IPs (such as PLLs, eFUSE, USB, PCIe, HTOL, and DRO)
• Debug DFT-Verification-related issues during the simulation
• Define and meet Code-coverage targets through targeted test-development and analysis.
• Actively support Post-SIlicon Bringup, Validation and Debug of DFX tests on Board and ATE.

• Bachelor s degree in Computer Science, Electrical Engineering or related fields and 7-12 years of related professional experience.
• Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 6-10 years of experience.
• The candidate must be proficient in System Verilog and UVM (Universal Verification Methodology).
• The candidate has to have good working understanding of DFT, test verification and pattern generation/simulation , and also ICL-PDL (Instrument Connectivity Language and Procedural Description Language) understanding
• Understanding of industry standards such as IEEE 1149.1 (boundary scan) and IJTAG (IEEE 1687).
• Familiarity with simulation tools, debug tools, and code-coverage environments.
• Strong problem-solving skills and attention to detail.
• Excellent communication and teamwork abilities.
• Experience with IP/DFX pattern generation and verification.

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