Staff Design Verification Engineer

About Marvell

Marvell s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell Semiconductor is seeking a highly skilled and experienced Staff Verification Engineer to join our dynamic team. The ideal candidate will have extensive experience in verification methodologies with a strong emphasis on Ethernet, SERDES, and UVM. As a Staff Verification Engineer, you will play a critical role in ensuring the quality and reliability of our cutting-edge semiconductor products.

What You Can Expect

• ASIC/IP design verification engineer responsible for the verification and evaluation of digital circuits in high speed data communication ICs.
• Involve in verification plan development, test environment setup , modeling, test-case development and execution.
• Responsible for block and/or chip level verification and verification of PCIE, Ethernet, Serdes PHYs functions using UVM methodology, System Verilog.

What Were Looking For

• Bachelor s degree in Computer Science, Electrical Engineering or related fields and 5-8 years of related professional experience.
• Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
• Must have good digital logic understanding and fundamentals of digital design.
• Candidate must have excellent skills in digital logic verification and hardware description language (VHDL or Verilog),
• Strong knowledge in object oriented programming using languages such as SystemVerilog
• Must have hands on experience in hardware verification methodologies such as UVM or OVM,
• Must be familiar with verification test planning and coverage driven verification closure, Verification strategies for directed and randomized testing and assertions
• Must have good experience in using simulation tools and proficiency in simulation debug techniques.
• Strong knowledge / experience in building the verification environment from specification and should have spec to hardware bring-up experience.
• Must have hands on knowledge on test-bench development and automation, bug tracking, and regression mechanisms
• Experience in High Speed SerDes, clock data recovery based PHYs, Asynchronous clock domain crossing verification.
• IP architecture and verification knowledge
• Experience in scripting languages such as Perl and operating system Linux
• Gate level simulation and AMS simulation knowledge
• Experience with Cadence or any other industry tools
• Should be a good team player
• Good communication skills and quick learning ability.
• Knowledge of standard configuration management system like CVS or SVN

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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