Principal Engineer, RTL ASIC Design

About Marvell

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Your Team, Your Impact

Infrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the award-winning OCTEON Fusion-M product families. The SoC family of multi-core CPU processors and Radio Access SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform. As part of the Infrastructure Processor unit at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers specifications whether they re a major telecom organization or automotive company, etc.

What You Can Expect

• Define the sub system architecture, micro-architecture and register specification for highly complex SoCs. Drive and participate in specification writeup
• Conduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers
• Implement a specification using RTL coding techniques and best practices
• Work with third party vendors to define customization requirements of third party IPs (controller, PHY, etc. )
• Work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff.
• Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug
• Help develop and/or evaluate design and verification methodologies and participate in improving existing ones
• Collaborate with and provide guidance to the post silicon and software teams for prototype bring up and performance tuning
• Provide mentorship to the more junior team members

What Were Looking For

• Bachelor s degree in Computer Science, Electrical Engineering or related fields and 12 -20 years of related professional experience.
• Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10-18 years of experience.
• Experience in creating architectural, micro-architectural, and register specifications.
• Verilog/System Verilog RTL coding with System Verilog assertions
• Well-versed in all stages of the ASIC design flow (including specification, architecture and design implementation, prototype bring-up)
• Expertise in high speed protocols (Ethernet).
• Should have worked on Full Chip Integration of Complex SoC design.
• Has worked on complex chips such as network processors, CPUs , GPUs , NOCs , Switches , Machine Learning SoCs etc. owning full chip, subsystem and block level architecture and design
• Expertise in any of the following domains would be a big plus: networking, embedded systems architecture, computer architecture, machine learning accelerators
• Experience with scripting in Perl/Python/Shell

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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