Analog Design, Manager

• This role involves analyzing various mixed signal techniques for dynamic and static power reduction, performance enhancement and area reduction. You d leverage your strong understanding of circuit simulation and circuit layout as we'll as knowledge of bipolar, CMOS, passive structure, and interconnect failure modes.
• You will be part of a strong development team in the area of High Speed PHYSICAL Interface Development.
• You will develop Analog Full custom circuit macros, ie, Analog front-end transceivers, voltage/current-mode drivers , delay-locked loop, phase-locked loop, Regulators, Equalizers (CTLE, FFE, DFE), Impedance calibrators, serializer , De-serializers , voltage-controlled oscillator, phase interpolator, bandgap reference, Clock data recovery circuits, Injection locked Loop needed for High Speed PHY IP, in planer and fin-fet CMOS technology.
• You will build and manage key analog design talent as a team to grow business impact in execution of design projects and nurture problem solving skills.
• You will be working with experienced set of teams locally and with people from various sites spread across globe.

Key Qualification:

• BE +10 years of relevant experience / MTech+8 years of relevant experience in mixed signal analog , custom circuit design , >2years experience in leading & mentoring engineering teams , educational qualifications in Electrical/Electronics/VLSI Engineering or other relevant field of study

• CMOS circuit design fundamentals, device physics, basic understanding of layout and parasitic extraction, spice simulation, sub-micron design methodologies, PLL/DLL, Voltage Regulators, data converters, Equalizers, Impedance calibrators.

• Analog transistor level circuit design in nanometer technologies.

• Familiarity Multi Gbps range High speed designs

• Can micro architect circuit from specifications, can create simulation benches to verify the specification, can understand and debug circuit.

• Should have basic understanding of layout and parasitic extraction

• Comfortable with spice simulations and various sub-micron design methodologies.

• Familiarity Multi Gbps range High speed designs and familiarity with such specs.

• Familiarity Multi Gbps range High speed design of clock and datapath

• Full custom design of high speed datapath using digital /cmos logic cells , handcrafting high performance clock path and verifying timing margins using spice and STA tools

• Familiarity with esd & latchup design verification in mixed signal analog design, crosstalk coupling impact on timings .

• Familiarity with automation / Scripting language