Design Verification Engineer - System Verilog

Job Title : Design Verification Engineer

Location : Bangalore, India

Experience : 4 -10 years

Notice Period : Immediate to 90 days

Job Type : Full-Time

About the Role :

As a Design Verification Engineer, you will play a crucial role in ensuring the functional correctness and quality of our digital IC designs. You will lead a team of verification engineers, develop comprehensive testbenches, and execute verification plans to identify and address design defects.

Your expertise will be instrumental in delivering high-quality products that meet stringent performance and reliability requirements.

Responsibilities :

Team Leadership : Lead and mentor a team of design verification engineers, ensuring efficient project execution and delivery of high-quality results.

Verification Expertise : Demonstrate a strong understanding of Verilog, System Verilog, and the UVM methodology.

Testbench Development : Have hands-on experience in developing UVM-based testbenches and C-based verification environments.

Protocol Expertise : Be proficient in HSIO protocols such as PCIe, DDR5, HBM, USB, or low-power simulations (UPF).

Debugging Skills : Possess exceptional debugging skills to identify and resolve verification issues efficiently.

Programming Proficiency : Have a solid foundation in programming concepts and languages.

Qualifications :

- Bachelor's or Master's degree in Electrical Engineering or a related field.

- 4 -10 years of experience in design verification, with a focus on digital ICs.

- Proven track record of leading verification teams and delivering successful projects.

- In-depth knowledge of Verilog, System Verilog, and the UVM methodology.

- Experience in developing testbenches for complex digital designs.

- Proficiency in HSIO protocols and low-power verification techniques.

- Strong problem-solving, debugging, and analytical skills.

- Excellent communication and collaboration skills.

Additional Preferred Skills :

- Experience with verification tools (e.g., QuestaSim, VCS).

- Knowledge of scripting languages (e.g., Python, Perl) for automation.

- Familiarity with formal verification techniques.