Design For Testability Engineer

Role : DFT

Location : Bangalore

Experience: 3 - 15 Yrs

Employment Type : Full Time, Permanent

Working mode : Regular

Notice Period : Immediate - 15 Days

Key Responsibilities :

DFT Methodology Expertise :

- Deep understanding of DFT methodologies, including scan, ATPG, MBIST, JTAG, BSCAN, and PG.

- Proficiency in industry-standard EDA tools for DFT implementation (e.g., Synopsys, Cadence, Mentor Graphics).

Design Integration :

- Collaborate with design teams to integrate DFT solutions into chip designs, ensuring testability and manufacturability.

- Analyze design specifications and requirements to identify DFT needs.

Test Pattern Generation :

- Develop and generate test patterns using ATPG tools to detect and isolate faults.

- Optimize test patterns for coverage, fault detection, and test time efficiency.

DFT Verification :

- Perform DFT simulations and analysis to ensure correct functionality and coverage.

- Identify and debug DFT-related issues.

Low-Power Design and PHY-LP Integration :

- Experience with low-power design techniques and PHY-LP integration is a plus.

- Understand the impact of DFT on power consumption and performance.

Qualifications :

- Bachelor's or Master's degree in Electrical Engineering or Computer Science.

- 3-15 years of experience in DFT engineering.

- Strong understanding of digital circuit design and testing principles.

- Proficiency in scripting languages (e.g., Perl, Python).

- Excellent problem-solving, analytical, and debugging skills.

- Strong communication and interpersonal skills.

- Ability to work independently and as part of a team.

Preferred Skills :

- Experience with advanced DFT techniques, such as memory BIST, embedded core testing, and mixed-signal DFT.

- Knowledge of semiconductor manufacturing processes and defect mechanisms.

- Familiarity with yield analysis and defect diagnosis tools.