AMS Verification Engineer (6-15 yrs)

Experience range : 6-15 Yrs

Location : Hyderabad

Availability : Immediate - 30 days

AMS Verification | Job Description

Responsibilities:

- To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs.

- Leading a project for AMS requirements is a value add.

- Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools

- Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus.

- Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS)

- Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus

- Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected

- Experience working on AMS Verification on multiple SOC's or sub-systems

- Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus

- Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment

- Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations

- Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows.

- Develop and execute top-level test cases, self-checking test benches and regressions suites

- Developing and validating high-performance behavior models

- Verifying of block-level and chip-level functionality and performance

- Team player with good communication skills and previous experience in delivering solutions for a multi-national client

- Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience

- Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc.

- Ability to extract simulation results, capture in a document and present to the team for peer review

- Supporting silicon evaluation and comparing measurement results with simulations

- UVM and assertion knowledge would be an advantage