Lead Software Engineer

Position: Lead Software Engineer

Location: Bangalore

Experience: 4-6 Years

Job Description

Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on Cadence s Genus Synthesis Solution product. Genus is a complete product that encompasses logic synthesis and physical design. The product breadth means we are looking for skilled and motivated candidates with backgrounds in logic synthesis, word-level synthesis, static timing analysis, computer architecture, verification, RTL compilation, placement, power analysis, routing, extraction, and optimization. You will be part of a team responsible for creating the innovative technologies required for technology leadership in this space. Development responsibilities include designing, developing, troubleshooting, debugging and supporting the Genus software product.

Job Responsibilities:

The role s day to day responsibilities cover:

R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power.

This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don t know what the answers are when we start out!

Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills.

Job Qualifications:

• Extensive experience developing large, high-quality, object-oriented C++ based applications is required

• Extensive experience with debugging and tuning of C++ code is required

• Expertise in data structures and algorithms is required

• Experience and understanding of EDA timing concepts and time constraints (SDC) is highly desirable

• Experience developing multi-core applications on Linux is highly desirable

• Experience developing on Linux with gcc is desirable

• Hardware knowledge and background in RTL design and/or verification is highly desirable.

Position Qualifications:

• B.E. in EE/ECE/CS or Equivalent

• Good understanding of Digital Electronics.

• Prior knowledge of Verilog and STA tools required.