IP Design Verification Engineer

Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment.

Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.

Bachelors or Masters from Engineering Background and Preferably from IIT, NIIT or Top ranked Institutes.

Minimum Qualifications: Strong coding experience in perl, python (one of the programming languages).

Strong in system Verilog 1-2 years' experience on AMBA protocols. Strong in computer architecture.

Preferred Qualifications:

0-1 feature bring up of any protocols. Incremental updates to checker (protocol checkers, bridge checkers) and VIP integration aligning with feature bring up. Configurable IP verification.

Test bench architecture.

Familiarity with test planning.