IP Design Verification Engineer

IP Verification Engineer: Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.

Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Objectives of the position

Own and deliver the functional verification of Mixed Signal IPs including regression debug and Coverage closure.

Critical thinking on Technical issues and ability to come up with improvements in existing testbench/verification solutions

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 5 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 7 years of relevant industry experience.
• Experience: Relevant ASIC Validation experience in front end processes including verification of design blocks (IP) for system-on-chip (SoC) components.Experience in system verilog, and/ OVM or UVM based verification methodologies.
• Experience in one/more of the following areas DDR/LPDDR/HBM or any complex protocol and /or AMBA standards (AXI, APB etc.).
• Knowledge of scripting, SVA, formal verification is added advantage .
• Experience in verification of Mixed signal IPs are plus but not mandatory.
• Knowledge of considerations for performance, power and cost optimization is desirable.
• Expected to be thorough with general verification concepts with System Verilog/OVM/UVM- Writing test cases,checkers and making scoreboard/infrastructure changes to the environment.
• Ownership/coding/enhancement of functional scoreboards/agents/sequences/monitors.
• Responsible for understanding architecture spec and deriving test cases / test plans.
• Need to be a key team player, while being highly energetic and motivated, independent and self-driven (with minimal mentoring/handholding)- Expected to define functional coverage/code/hit it through sequence enhancement and newer/directed test. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
• Working exp on verification of PHY or IO Interconnect is plus. preferred not mandatory