Platform Validation and Debug Engineer

Participates in failure analysis and platform debug to root cause failures across platform domain areas like Power Management, Memory, Reset, PCIe, CXL, RAS, Security, Manageability.

Defines, develops, and executes platform-based validation environments, test suites, and plans and drives characterization and yield enhancements to ensure testability, manufacturability, and production of integrated circuits.

Develops debug methodologies, complex software programs for new device features, and design validation vectors.

Evaluates components to ensure performance meets specifications and delivers optimal match of component requirements with production equipment capability.

Applies knowledge of platform level tools and techniques to conduct root cause analysis, failure analysis, troubleshoot, and debug cross discipline and complex integration issues of the platform.

Documents test results, analyzes test data, communicates results while continually improving test methods.

Conducts integrated platform level validation, verifies that the product meets quality and/or reliability attributes and complies with applicable specifications.

Drives product requirements as needed by customers to ensure necessary capabilities for platform validation activities.

Collaborates with multiple teams across board design, power, platform design, development, and debug to ensure all features are validated and optimized timely.

Works with product development engineers and end customers as first points of contact to support debug, root cause analysis, and customer platform issues.

Qualifications
You must possess the minimum qualifications to be initially considered for this position- Candidate must possess a master's or bachelor's degree in electrical or computer engineering or a related discipline

- Experience on Intel architecture and debug, failure analysis is a plus

- Good problem solver with good hands-on skills for programming using Python / Unix Shell scripting/ C and able to do source code level debug firmware/platform issues and build scripts for automating test content would be an advantage.

-Good understanding of Intel Architecture Operating System Drivers, BIOS flows, compute/memory/ storage performance design fundamentals

Engineers focus will be to Develop and implement validation strategies, including defining the number of cycles required to meet QRC (Quality, Reliability, and Compliance) criteria.

Create new test content and automate testing based on customer use cases to identify and address coverage and interoperability gapsin Reset and PM domain.

Provide expert debugging and support for the enablement of various custom features and functionalities.

Collaborate with internal teams to ensure feature stability and lead task forces to resolve DPMO and reset issues.

Experience must also be inclusive of

1. Platform validation and or debug experience with Intel Architecture and Server Platform experience.

2. Familiarity with debugging tools such as Intel ITP based environments, protocol analyzers, logic analyzers, power meters and DAQs

3. Must be willing to engage with external customers when needed

4. Experience with Python or Unix Shell script development is an advantage.