Principal Engineer Chip Verification

Write verification plans to meet these requirements after closealignment with other verification teams for proper work split accordingto mutually acceptable verification assignment..
Execute the verification plan by developing C/C++ test cases andSystem Verilog/UVM test bench components and by integrating 3rd partyVIP components..
Simulate and debug at RTL, Unit Delay, and Gate Level usingappropriate tools and flows including Emulator, Portable Stimulus, orFormal methodologies for functional and toggle coverage closure..
Lead a team technically through exploring new environment andidentifying potential enhancement areas through new methodology..
Identify and setting mid/long term goals based on benchmarking againstindustry standards..
You are best equipped for this task if you have:.
Understand the usage of tools like Xcelium, Spectre(X) and Simvision.
Strong foundational knowledge of digital/mixed-signal design verification..
Knowledge and hands-on experience of System Verilog and UVM..
Exposure to version-controlling (eg, Git/Bitbucket, ClearCase, CVS,SVN) and bug-management schemes.
Self-motivated, flexible and with strong interpersonal skills.
Good communication with interpersonal skills and is a good team playerwho is able to work well with both internal and external partners..
Candidate who has more relevant working experience will be consideredfor a more senior position.
It is a plus to have:.
Hands-on experience in hardware-software debugging at the system orapplication level..
Hand-on experience with gate-level-simulations and withdebugging/troubleshooting skills is a plus.
Understanding of UPF context of analog/transistor level.
Basic analog knowledge for debugging purposes..
Experience in automotive industry in Functional Safety ISO26262 andCybersecurity ISO21434 are advantageous..