Senior Specialist PDK Development

• Familiar with full-custom and semi-custom design flows and PVmethods/concepts
• Strong layout and design verification experience
• Strong background in semiconductor device physics
• Good understanding of IC fabrication process and IC Design Process
• Good understanding of electronic circuits and physical verification anddigital implementation concepts

• Development and maintenance of Physical Verification ruledecks
• Development and maintenance of techfiles used in digital implementationtools
• Development and maintenance of fill runsets and their integration todigital implementation tools

You are best equipped for this task if you have:

• Education - BE / B.Tech / ME / M.Tech \ MS in Electronics / ComputerScience
• Experience - 1 to 3 years
• Expertise in developing physical verification rule decks (using Calibresvrf + PERC)
• Expertise in developing techfiles for digital implementation tools fromSynopsys /Cadence (ICC2 /Innovus)
• Expertise in developing PV runsets for fill using Synopsys\ / Cadence(ICV\ / PVS\ / Pegasus)
• Expertise in programming\/scripting languages w.r.t PDK development andQA
• TCL, PERL, PYTHON, Shell scripting
• Exposure to Cadence Virtuoso environment and SKILL programming
• Exposure to version control tools SVN, CLEARCASE, PERFORCE
• Exposure to issue tracking tools (JIRA)
• Exposure to working with multi-cultural and cross functional teams
• Proactive with good communication (assertive) and interpersonal skills
• Customer orientation is a must
• Avid programmer with excellent debugging skills to diagnose and deviseworkarounds for PDK\/flow\/design issues
• Demonstrate strong teamwork, communication skills and work ethics