RTL Design Architect Engineer

Responsibilities:

Architecture exploration and Micro-architecture development
RTL design and integration for 5G NR UE systems using Verilog/System Verilog
Collaboration with multi-discipline teams to integrate, test and debug the designs on FPGAs
Required Qualifications:
Master's/Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or equivalent practical experience
Skills/Experience Required
Strong Domain Knowledge on RTL Design, implementation, and integration for FPGA based designs.
Experience with RTL coding using Verilog/System Verilog.
Proficiency in complete FPGA design flow.
Experience with protocols like AXI4-stream and AXI4.
Exposure in scripting (Python/TCL).
Strong debugging capabilities at RTL simulation and FPGA Emulation.
Proficiency in version control tools like GIT.