Senior Engineer - Design Verification

• Analog Devices is seeking Digital Design Senior verification Engineer, who will be responsible for design verification of highly integrated solutions and products in a multifunctional team.
• You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units.

About the Role

• Key member of design verification team responsible for SOC or subsystem design pre silicon verification
• The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products
• As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI
• The candidate is also encouraged to participate in cross company technical initiatives as we'll as patent and publish work where possible

Responsibilities

• End to End verification ownership of IP or Subsystem or SOC level
• Verification of complex microprocessor designs, neural nets and high-speed peripherals using leading edge verification methodologies.
• UVM testbench architecture development and implementation of DV flows, methodology
• Defining testplans, tests and verification methodology for block / subsystem and chip-level verification. Working with the design team in generating and reviewing testplans and closure of code and functional coverage
• Working with other verification team disciplines like emulation, FPGA and Firmware teams to determine correct functionality.
• Formal verification of IP s and Subsystems
• NOC, Interconnect verification
• Performance verification and Performance analysis of complex SOCs end to end scenarios
• System level use case scenarios definition, coding and verification
• Innovating verification solutions to hit deliverable schedules.
• The chance to be exposed to and learn state of the art verification techniques such as formal, emulation, portable stimulus and virtual platforms.
• Come up with verification strategy for a product after going through product requirements and design specifications.

Requirements

• B.Tech/M.Tech with 5+ years of industry experience in Digital Pre Silicon verification.
• Good understanding of SOC/Subsystem design concepts and design architectures.
• Hands on experience in developing, updating and debugging of Verilog, SV-UVM , SOC level testbenches is a must.
• Experience in closing the verification of block, subsystem level verification using industry standard metrics like code and functional coverage is a must.
• Expertise on NOC, Bus and Interconnect Verification. Coverage Analysis and improvements
• Test Bench, TB, environment, architect and implement verification flow and methodology
• Power aware verification with UPF, Power analysis and Power optimization
• Knowledge on Formal verification is an added advantage
• Gate level Simulation with timing annotated
• Strong knowledge of test-plan generation, coverage analysis transaction level modeling, pseudo and constrained random techniques with System Verilog
• In-depth knowledge of SV-UVM and debugging of testbenches is a must.
• Assertion and formal knowledge is an advantage.
• Knowledge of microprocessor cores such as ARM, RISC-V, Tensilica , Neural Network, GPU Cores is a plus.
• System Verilog, C/C++, System C, TCL/Python/shell-scripting
• Exceptional interpersonal and communication skills, collaborate and influence innovative design development/verification methodologies to wider team spread across the globe.
• Quick to adopt new technologies with good problem-solving skills.