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2 Delancey Technologies Jobs
Design Verification Engineer:
Delancey Technologies
posted 5mon ago
Job Description
Knowledge of atleast one scripting language like Python, Perl, Shell, TCL
Should have good documentation/communication skills and be able to work with multi-functional, multi-site teams
Mid-level level:
- 2 to 4 years of experience in Verification with B.E/B.Tech/M.E/M.Tech.
- Good knowledge on Verilog/System Verilog/UVM/OVM.
- Knowledge of at least one scripting language like Python, Perl, Shell, TCL
- Knowledge of at least one industry standard protocols like Ethernet, PCIe, USB, SATA, NVMe, AMBA, ARM, RISC CPUs etc.,
- Able to work on functional coverage modelling and Code coverage analysis.
- Experience in GLS will be added advantage.
- Should have good documentation/communication skills and be able to work with multi-functional, multi-site teams
Senior level:
- 5 to 7 years of experience in Verification with B.E/B.Tech/M.E/M.Tech.
- Good knowledge on Verilog/SystemVerilog/UVM/OVM.
- Knowledge of at least one scripting language like Python, Perl, Shell, TCL
- Knowledge of at least one industry standard protocols like Ethernet, PCIe, USB, SATA, NVMe, AMBA, ARM, RISC CPUs etc.,
- Good RTL debugging skills.
- Expertise in independently creating detailed test plan with well-defined functional coverage goals.
- Hands on experience on GLS sims with SV UVM based env.
- DV planning and risk mitigation
- Communicate with all stakeholders (design, PD and HQ) for scheduled alignment, risk assessment and other responsibilities
- Support post silicon team, DFT and PD team for characterization, vector generation and power analysis
Employment Type: Full Time, Permanent
Functional Areas: Other
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What people at Delancey Technologies are saying
Design & Verification Engineer salary at Delancey Technologies
reported by
1
employee
with 2
years exp.
₹4.3
L/yr - ₹5.5
L/yr
35%
less
than the average Design & Verification Engineer Salary in India
View more details
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