DFT Engineer (4-15 yrs)

SALARY : 10LPA - 35LPA

We are recruiting One of Our Indian Based MNC Client

Client - Indian Based MNC Client

Type of Job - Full Time

Type - Hybrid

Notice Period- Not more than 45 Days with serving candidates

Role : DFT Engineer

Experience : 4+ Years

Locations : Bangalore/Kochi/Vizag/Ahmedabad

Mandatory Skills : DFT Experience Required

Job Title : DFT (Design for Test) Engineer

Job Overview :

As a DFT Engineer, you will be responsible for implementing and verifying design-for-testability (DFT) features in complex ICs such as SoCs, ASICs, or custom chips. Your role involves developing test architectures, implementing test structures, and ensuring the testability of the design for manufacturing. You will collaborate with RTL designers, physical design teams, and test engineers to deliver high-quality and robust testable designs that meet manufacturing test requirements and ensure product quality and reliability.

Key Responsibilities :

DFT Architecture & Planning :

- Define and implement DFT architecture for SoC, ASIC, or FPGA designs to meet test coverage goals.

- Develop and optimize test strategies including scan, BIST (Built-In Self-Test), and boundary scan (IEEE 1149.1/JTAG).

- Collaborate with cross-functional teams to integrate DFT requirements into the overall design.

DFT Implementation :

- Implement various DFT techniques such as scan insertion, ATPG (Automatic Test Pattern Generation), boundary scan, and memory BIST.

- Integrate DFT structures into the RTL code and verify the correctness of the design using simulation and formal methods.

- Work closely with the physical design team to ensure successful insertion of test structures into the final layout.

Test Pattern Development :

- Generate and validate test patterns using ATPG tools to ensure high fault coverage for manufacturing tests.

- Ensure that the generated test patterns meet testability requirements and are optimized for production test cost and time.

- Debug test patterns and work with silicon validation teams to ensure they function correctly on the final product.

Fault Coverage & Verification :

- Perform fault coverage analysis to identify test coverage gaps and develop strategies to close them.

- Ensure that the design meets or exceeds target test coverage and test cost goals, optimizing test time and yield.

- Conduct simulations to verify the functionality and integrity of DFT structures.

Post-Silicon Support :

- Support post-silicon testing and bring-up by diagnosing test failures and debugging issues related to DFT features.

- Work with test engineers to optimize test programs for volume production and yield improvement.

- Provide feedback to design teams to improve DFT methodologies for future products.

DFT Tooling & Automation :

- Work with industry-standard DFT tools such as Synopsys DFTMAX, Mentor Tessent, Cadence Modus, or similar.

- Automate DFT flows and test pattern generation processes to improve efficiency and scalability.

- Stay current with evolving DFT techniques, tools, and industry best practices.

Collaboration & Communication :

- Collaborate with design, verification, and test engineering teams to align DFT goals with overall project objectives.

- Communicate test coverage results and DFT progress to stakeholders and project management.

- Ensure DFT documentation is complete and well-maintained for handoff to manufacturing and test teams.

Required Skills & Qualifications :

Technical Expertise :

- Strong experience in DFT techniques such as scan insertion, ATPG, JTAG, boundary scan, and BIST (Logic BIST and Memory BIST).

- Proficiency with DFT EDA tools such as Synopsys DFTMAX, Mentor Tessent, or Cadence Modus.

- Solid understanding of fault modeling, fault coverage metrics, and test pattern generation.

- Experience in Verilog/VHDL for RTL coding and modifications related to DFT structures.

- Strong understanding of ASIC/SoC design flows including synthesis, timing closure, and physical design integration.

Soft Skills :

- Strong communication and collaboration skills to work effectively across teams.

- Detail-oriented with excellent problem-solving skills to address testability challenges.

- Ability to work in a fast-paced environment and manage multiple projects simultaneously.

Preferred Qualifications :

- Experience with low-power DFT techniques and power-aware ATPG.

- Knowledge of DFT for advanced process nodes such as 7nm or 5nm.

- Familiarity with post-silicon debug and failure analysis techniques.

- Understanding of DFM (Design for Manufacturability) methodologies and strategies to improve yield.

- Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Education & Experience :

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

- 3-7 years of experience in DFT implementation for SoCs, ASICs, or custom ICs.

Note - Please share an updated copy of your resume while replying to this email with the below information.Interested Candidates

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