Principal Engineer: ASIC Verification (Global R&D Sol from Scratch)

Dear Applicants

We, Cyient is hiring for Principal Engineer: ASIC Verification for End to End Offshore-Onshore Model based Global Product R&D Solution Opportunity.

Base Location: Bangalore & Hyderabad

Experience Range: 15-25 Yrs

Job Description:

Looking for an experienced senior verification engineer with > 15 years of experience in ASIC/SOC/IP/block level functional verification using system verilog/UVM.

The ideal candidate will have strong command of UVM, advanced UVM and system verilog
Key responsibilities:

Develop a comprehensive test plan, complete test-bench and robust verification environment including interface agents and scoreboard in UVM possess deep knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB

Strong debugging skills to address TB issues quickly and test failures.

Take responsibility for verification closure by addressing coverage and managing bug reports
proficiency in using industry standard verification tools such as Questa, VCS or ModelSim

Experience with scripting languages like python, perl or TCL for automation tasks

Manage a team of 6 to 7 Engineers, Interact with the customer on the tasks and status updates

Experience working with Japan customer is a must

Japan speaking a mandatory skill

Thanks and Regards

Rajani Kant Sharma

Sr Recruiter: Global Lateral Hiring: Semicon Vertical

Cyient