DFX Verification Engineer - RTL/GLS (5-9 yrs)

Key Responsibilities :

- Perform RTL verification and debugging for complex designs.

- Conduct Gate-Level Simulations (GLS) and debug issues effectively.

- Develop and optimize Verilog code for design verification.

- Ensure thorough verification in Testmode and collaborate with design teams for debugging.

- Work with JTAG for design and verification activities.

- Contribute to test case development and debugging strategies.

Good to Have :

- Experience in pattern generation and validation workflows.

- Hands-on expertise in Silicon debug to ensure robust design delivery.

Key Skills :

- Strong knowledge of RTL design and verification processes.

- Proficiency in Verilog and debug methodologies.

- Understanding of JTAG protocols and Testmode operations.

- Analytical problem-solving and teamwork skills.