Static Timing Analysis Lead - Clock Domain Crossing (10-15 yrs)

Position : STA Lead (Static Timing Analysis Lead)

Experience Required : 10-15 years

Location : Bangalore / Hyderabad

Must-Have Skills : Primetime, Tempus, Static Timing Analysis (STA)

Role Overview :

As an STA Lead, you will be responsible for overseeing and leading static timing analysis for digital designs. You will work closely with design, verification, and implementation teams to ensure that timing closure is met for complex SoC designs. You will leverage tools like Primetime and Tempus for accurate timing signoff and work on all aspects of the timing flow, including clock-domain crossing (CDC), setup/hold violations, and optimizations.

Key Responsibilities :

- Lead and mentor the STA team in performing static timing analysis on complex digital designs.

- Work on end-to-end STA flow from RTL through synthesis, placement, and routing, including post-route STA sign-off.

- Ensure proper clock-domain analysis, timing closure, and validation at various stages of the design process.

- Perform timing signoff using Primetime / Tempus to ensure the design meets performance, power, and area requirements.

- Perform and analyze timing reports, identify potential issues, and suggest solutions for optimization.

- Debug and resolve timing violations such as setup, hold, recovery, and removal violations.

- Provide guidance on Clock Tree Synthesis (CTS), clock gating, power optimization, and timing optimization.

- Interact with cross-functional teams (RTL designers, synthesis engineers, place & route engineers) to resolve design timing issues.

- Validate timing across multiple corners (PVT) and ensure robustness in various environmental conditions.

- Contribute to improving STA methodology, scripts, and flows for better performance and efficiency.

- Collaborate with verification teams to ensure comprehensive coverage of timing and functional correctness.

- Provide detailed feedback and reports to senior management and clients.

Must-Have Skills :

- In-depth knowledge of Static Timing Analysis (STA) concepts and methodologies.

- Proficient in using Primetime and/or Tempus for performing timing signoff and analysis.

- Solid understanding of synthesis, place & route tools, and timing closure.

- Strong hands-on experience with timing constraint generation and optimization.

- Expertise in analyzing and resolving setup/hold violations, clock domain crossings (CDC), timing corners, and timing ECOs.

- Experience in handling complex multi-clock designs and performing clock gating/optimization.

- Strong understanding of ASIC/FPGA design flow, including RTL to GDSII.

- Proficient in scripting languages like TCL, Python, or Perl for automating STA tasks.

- Good knowledge of high-speed design, clock tree synthesis (CTS), noise analysis, and timing analysis across corners.

- Familiarity with DFT (Design for Test) and related aspects in timing analysis.

- Ability to handle large-scale designs and provide optimized solutions for timing closure.

Preferred Skills :

- Experience with Power and Signal Integrity analysis.

- Knowledge of advanced process nodes (e.g., 7nm, 5nm).

- Familiarity with Design for Manufacturability (DFM) concepts and methodologies.

- Familiarity with Synopsys DSO.ai, Cadence Innovus, and Mentor Graphics tools.

Qualifications :

- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related fields.

- 10-15 years of experience in Static Timing Analysis or related roles in ASIC/SoC design.

- Prior experience leading an STA team is highly desirable.