Design Verification

We are looking for a highly skilled Design Verification Engineer with a deep understanding of functional verification and verification methodologies. The ideal candidate will have proven experience in verifying complex digital designs and a strong ability to develop verification plans and environments from the ground up. If you have a passion for debugging, problem-solving, and working with cutting-edge technologies, we would love to have you on our team.

Key Responsibilities:

• Constrained Random Functional Verification: Perform constrained random functional verification to ensure the functionality and correctness of designs.
• Verification Environment Development: Develop comprehensive test plans and create robust verification environments from scratch.
• Verification of Complex Blocks: Conduct verification of complex design blocks, ensuring correctness and completeness of the verification process.
• Regression and Coverage Closure: Handle regressions and coverage closure to ensure complete verification of designs.
• Gate-Level Simulations and Debugging: Execute gate-level simulations and resolve issues identified during the simulation process through effective debugging techniques.
• Problem-Solving and Analysis: Use strong analytical skills to debug and solve complex verification challenges efficiently.
• Independent and Proactive: Work independently, taking initiative to meet verification goals, and proactively address issues as they arise.
• Team Collaboration: Collaborate closely with cross-functional teams, providing regular updates on verification progress and working towards continuous improvement.

Preferred Qualifications:

• Interface Knowledge: Knowledge of key industry-standard interfaces, such as:
• I2C, UART, SPI, Ethernet, Video (DisplayPort, CSI/DSI), PCIe, and Audio I2S.
• Silicon Bring-up and Validation: Experience with lab silicon bring-up, validation, and production test support is highly desirable.

Required Skills & Experience:

• 5+ years of experience in design verification for complex digital systems.
• Strong understanding of functional verification methodologies, including constrained random verification, coverage analysis, and assertion-based verification.
• Experience in developing test plans, writing testbenches, and creating verification environments from scratch.
• Familiarity with gate-level simulation and debugging techniques.
• Proficiency in debugging complex issues and performing root cause analysis.
• Strong understanding of regression testing, coverage closure, and verification of complex blocks.
• Excellent communication, teamwork, and interpersonal skills to collaborate with design and verification teams.
• Ability to work independently, take ownership of tasks, and drive them to completion in a result-oriented manner.