Physical Design Lead

Job Location- Bangalore.

Position- Leadership role-Physical design .

Technical Skills:

• Should be able to handle Full chip/Block level PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design
• Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, STA, IR/EM checks and signoff DRC/LVS closure
• Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM
• Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM)
• Experience in lower tech node (less than 7nm)
• Good automation skills in PERL, TCL and EDA tool-specific scripting
• Able to take complete ownership for Block/sub-system for complete execution cycle
• Must have cadence/Innovus tools and team handling exp.

Qualification:

BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design

Experience 8+

Notice Period- Prefer Immediate or serving Notice period.

Interested can share CV sneha.s@acldigital.com