Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries.
Excellent hands-on P&R skills with expert knowledge in ICC/Innovus
Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure
Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes.
CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries.
Significant knowledge and preferably hands on experience on SoC STA, Power, Physical Verification and other sign-off.
Good problem-solving capabilities, proactive, hardworking with strong interpersonal skills.
Bachelor's Degree in Electrical, Electronics or Computer Engineering