Physical Design Engineer

Experience Required: 4 to 10 years

Key Responsibilities:

• Execute and optimize SoC Physical Design tasks across multiple technology nodes, including advanced nodes like 5nm for TSMC and other foundries.
• Hands-on implementation of Place and Route (P&R) using tools like ICC and Innovus.
• Contribute to all stages of Physical Design (PD) from Synthesis to GDSII, with a focus on:
• Floorplanning
• Placement
• Clock Tree Synthesis (CTS)
• Routing
• P&R
• Extraction
• IR Drop Analysis
• Timing closure
• Signal Integrity closure
• Participate in multiple chip tapeouts, handling top-level design challenges and advanced node requirements.
• Collaborate with CAD, Methodology, and IP teams to ensure smooth PD implementation and timely deliverables.
• Support SoC-level Static Timing Analysis (STA), Power Analysis, Physical Verification, and other sign-off processes.
• Identify and resolve design challenges effectively and efficiently.

Required Skills:

• Strong proficiency in ICC and Innovus tools for Physical Design tasks.
• In-depth knowledge of advanced technology node design (e.g., 5nm).
• Excellent problem-solving skills and the ability to manage complex design issues.
• Strong collaboration and communication skills to work effectively with cross-functional teams.

Education:

• Bachelor's Degree in Electrical Engineering, Electronics Engineering.

Preferred Qualifications:

• Hands-on experience in SoC-level STA, Power, and Physical Verification sign-offs.
• Involvement in multiple chip tapeouts, especially at advanced nodes.
• Knowledge of CAD and design methodology optimizations.

Ideal Candidate Profile:
The ideal candidate is a motivated professional with a strong technical foundation in Physical Design. They demonstrate the ability to handle complex design tasks with efficiency and actively contribute to the success of tapeouts at the latest technology nodes.