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Tessolve Interview Questions and Answers
27 Interview questions
An XOR gate can be constructed using AND, OR, and NOT gates to achieve the desired output.
XOR outputs true only when inputs differ: A=0, B=1 -> Output=1; A=1, B=0 -> Output=1.
Use two AND gates, one OR gate, and two NOT gates to create the XOR function.
The expression for XOR is: A XOR B = (A AND NOT B) OR (NOT A AND B).
Example: For inputs A=1, B=0, NOT B=1, NOT A=0; thus, (1 AND 1) OR (0 AND 0) = 1.
Analyzing circuit behavior to predict expected results based on given inputs and configurations.
Identify the type of circuit (e.g., combinational, sequential) to determine its behavior.
For combinational circuits, use truth tables to map inputs to outputs.
For sequential circuits, consider the state transitions and memory elements involved.
Example: In a simple AND gate, if both inputs are high, the output is high; o...
Basics of electrical circuits involve understanding components, laws, and circuit types for effective PCB design.
Components: Resistors, capacitors, inductors, diodes, and transistors are fundamental elements in circuits.
Ohm's Law: V = IR (Voltage = Current x Resistance) is crucial for analyzing circuits.
Series vs Parallel: In series, current is the same; in parallel, voltage is the same. Example: Christmas lights ...
SystemVerilog (SV) and UVM are essential for designing and verifying complex digital systems.
SystemVerilog is an extension of Verilog, adding features like classes, interfaces, and assertions.
UVM (Universal Verification Methodology) is a standardized methodology for verification using SystemVerilog.
UVM provides a base class library for creating reusable verification components, such as agents and testbenches.
Examp...
SystemVerilog (SV) and UVM are essential for designing and verifying complex digital systems.
SystemVerilog enhances Verilog with object-oriented programming features.
UVM (Universal Verification Methodology) provides a standardized framework for verification.
Example: Using UVM, you can create reusable testbenches for different designs.
SV supports assertions, which help in checking design properties during simulatio...
A 4:1 mux can be implemented using two 2:1 muxes by selecting one of the 2:1 muxes based on the select line.
Use one 2:1 mux to select between the two inputs of the second 2:1 mux based on the select line
Connect the outputs of the two 2:1 muxes to get the final 4:1 mux output
NAND gate can be implemented using a 2:1 multiplexer by connecting one input to select line and the other input to one of the data inputs.
Connect one input of the NAND gate to the select line of the 2:1 mux.
Connect the other input of the NAND gate to one of the data inputs of the 2:1 mux.
Connect the other data input of the 2:1 mux to ground.
The output of the 2:1 mux will be the output of the NAND gate.
A 58:1 mux can be implemented using 2:1 mux by cascading multiple levels of muxes.
Implement a 2:1 mux using 2 input lines and 1 output line.
Cascading multiple levels of 2:1 muxes can create a 4:1, 8:1, 16:1, and finally a 58:1 mux.
In this case, you would need 6 levels of 2:1 muxes to create a 58:1 mux.
Creating a dataframe and performing data manipulations in Python using pandas library.
Import pandas library
Create a dictionary with data
Convert dictionary to dataframe using pd.DataFrame()
Perform operations like filtering, sorting, grouping, etc.
Use a flip-flop to divide the frequency by 2.
Use a D flip-flop with the input connected to the clock signal and the output connected back to the D input.
The output frequency will be half of the input frequency (25MHz).
Tessolve Interview Experiences
57 interviews found
Anonymous
I appeared for an interview in Dec 2024.
(2 Questions)
- Q1. Sv hvm questions on constraiants and assertions
- Q2. Questions on resume projects
(2 Questions)
- Q1. Questions on protocols
- Q2. Sv uvm questions
- Ans.
SystemVerilog (SV) and UVM are essential for designing and verifying complex digital systems.
SystemVerilog enhances Verilog with object-oriented programming features.
UVM (Universal Verification Methodology) provides a standardized framework for verification.
Example: Using UVM, you can create reusable testbenches for different designs.
SV supports assertions, which help in checking design properties during simulation.
Exa...
(2 Questions)
- Q1. Salary and pckge discussion
- Q2. Details on client interview
(2 Questions)
- Q1. Projects and challenges
- Q2. Sv uvm basics
- Ans.
SystemVerilog (SV) and UVM are essential for designing and verifying complex digital systems.
SystemVerilog is an extension of Verilog, adding features like classes, interfaces, and assertions.
UVM (Universal Verification Methodology) is a standardized methodology for verification using SystemVerilog.
UVM provides a base class library for creating reusable verification components, such as agents and testbenches.
Example: A...
I applied via Campus Placement and was interviewed in Nov 2024. There was 1 interview round.
(4 Questions)
- Q1. Implement nand gate using 2:1 mux
- Ans.
NAND gate can be implemented using a 2:1 multiplexer by connecting one input to select line and the other input to one of the data inputs.
Connect one input of the NAND gate to the select line of the 2:1 mux.
Connect the other input of the NAND gate to one of the data inputs of the 2:1 mux.
Connect the other data input of the 2:1 mux to ground.
The output of the 2:1 mux will be the output of the NAND gate.
- Q2. Implement a 4:1 mux using 2:1 mux
- Ans.
A 4:1 mux can be implemented using two 2:1 muxes by selecting one of the 2:1 muxes based on the select line.
Use one 2:1 mux to select between the two inputs of the second 2:1 mux based on the select line
Connect the outputs of the two 2:1 muxes to get the final 4:1 mux output
- Q3. Implement a 58:1 mux using 2:1 mux and how many mux are required?
- Ans.
A 58:1 mux can be implemented using 2:1 mux by cascading multiple levels of muxes.
Implement a 2:1 mux using 2 input lines and 1 output line.
Cascading multiple levels of 2:1 muxes can create a 4:1, 8:1, 16:1, and finally a 58:1 mux.
In this case, you would need 6 levels of 2:1 muxes to create a 58:1 mux.
- Q4. Projects in the resume
- Ans.
My projects showcase a blend of innovative digital design techniques and practical applications in various domains.
Designed a low-power digital filter for audio processing, improving efficiency by 30%.
Developed a high-speed data acquisition system using FPGA, achieving 1 Gbps throughput.
Implemented a custom ASIC for image processing, reducing latency by 50% compared to previous designs.
Collaborated on a team project to...
Interview Preparation Tips
Basics core questions MCQ totally 50 questions
(2 Questions)
- Q1. Technical hr round Asked about basic technical questions like what is resistance,a tive elements and passive elements,rectifer and draw and explain full wave rectifier circuit
- Q2. Self intro and releted
(1 Question)
- Q1. General hr Asked generally
Interview Preparation Tips
Aptitude with general knowledge
(1 Question)
- Q1. Basic of electronics and electrical
(1 Question)
- Q1. Family background and few situational questions
(1 Question)
- Q1. Round with vice president
I applied via Company Website and was interviewed in Jul 2024. There were 2 interview rounds.
Aptitude level is easy to medium
(4 Questions)
- Q1. Questions on basic electronics concepts like semiconductors, transistors etc
- Q2. How the current flow in transistors
- Ans.
Current flow in transistors is controlled by the voltage applied to the base terminal.
Transistors are three-terminal devices: emitter, base, and collector.
Current flows from the collector to the emitter when a voltage is applied to the base.
The amount of current flowing through the transistor is determined by the base current.
Transistors can be used as amplifiers or switches in electronic circuits.
- Q3. Personal introduction
- Q4. About my projects
I applied via Company Website and was interviewed in Jul 2024. There were 2 interview rounds.
This round is classified as easy to medium.
(2 Questions)
- Q1. How the current is flowed in the semiconductor
- Ans.
Current flows in a semiconductor due to the movement of charge carriers, either electrons or holes.
Current flows in a semiconductor when charge carriers (electrons or holes) move under the influence of an applied electric field.
In an n-type semiconductor, current is carried by electrons, while in a p-type semiconductor, current is carried by holes.
The flow of current can be controlled by applying a voltage across the s...
- Q2. Questions on resistors,transistors etc
I appeared for an interview in Mar 2025, where I was asked the following questions.
- Q1. Prepare bascis of electrical circuits
- Ans.
Basics of electrical circuits involve understanding components, laws, and circuit types for effective PCB design.
Components: Resistors, capacitors, inductors, diodes, and transistors are fundamental elements in circuits.
Ohm's Law: V = IR (Voltage = Current x Resistance) is crucial for analyzing circuits.
Series vs Parallel: In series, current is the same; in parallel, voltage is the same. Example: Christmas lights (seri...
- Q2. Electronic devices and circuits
Vinay B C
Selected
(1 Question)
- Q1. Multiple C, C++ DSA Questions
Selected
I appeared for an interview before Feb 2024.
20 MCQ based questions on C programming. 2 coding based questions.
(3 Questions)
- Q1. Asked my knowledge on different types of sensors
- Q2. Questions on pointers in C Programming
- Q3. Embedded systems based basic questions.
Juhi Singh Padole
(1 Question)
- Q1. Tell me about yourself
- Ans.
I am a passionate and experienced Design Engineer with a strong background in mechanical engineering.
Graduated with a degree in Mechanical Engineering from XYZ University
Worked for 5 years at ABC Company designing innovative products
Proficient in CAD software such as SolidWorks and AutoCAD
Strong problem-solving skills and attention to detail
Passionate about staying updated on the latest design trends and technologies
(1 Question)
- Q1. Past experience
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