VLSI FIRST Bangalore / Bengaluru Design & Verification Engineer Salaries by 2 Employees (Updated 2025)

0 - 1 year exp.

₹4.1 Lakhs - ₹5.2 Lakhs

Low Confidence

Salary of majority employees

Fixed (89%)

₹4.1 Lakhs

Variable (11%)

₹0.5 Lakh

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Last Updated: 31 Jul 2024

Companies similar to VLSI FIRST for Design & Verification Engineer in Bangalore / Bengaluru

VLSI FIRST Design & Verification Engineer Salary

0 - 1 year exp. (AmbitionBox Estimate)

₹4.1 L/yr - ₹5.2 L/yr

Company name	Avg Annual Salary	Open Jobs
Wipro Design & Verification Engineer Salary 1 - 5 years exp. (46 salaries)	₹3.6 L/yr - ₹9.4 L/yr 17% more	2 job openings
Capgemini Design & Verification Engineer Salary 1 - 4 years exp. (42 salaries)	₹4 L/yr - ₹8 L/yr At par
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Tech Mahindra Design & Verification Engineer Salary 1 - 5 years exp. (33 salaries)	₹3.5 L/yr - ₹10.4 L/yr 27% more
HCLTech Design & Verification Engineer Salary 1 - 4 years exp. (8 salaries)	₹4.5 L/yr - ₹6.5 L/yr 8% more
Accenture Design & Verification Engineer Salary 1 - 4 years exp. (4 salaries)	₹5.8 L/yr - ₹9.3 L/yr 45% more
TCS Design & Verification Engineer Salary 2 - 3 years exp. (4 salaries)	₹4 L/yr - ₹6.8 L/yr 24% more
Larsen & Toubro Limited Design & Verification Engineer Salary 2 - 3 years exp. (3 salaries)	₹5 L/yr - ₹5.5 L/yr 15% more

Design & Verification Engineer salary at VLSI FIRST ranges between ₹4.1 Lakhs to ₹5.2 Lakhs per year for employees with less than 1 year of experience. Salary estimates are based on 2 latest salaries received from various employees of VLSI FIRST.

Salary related reviews for VLSI FIRST

RTL Design And Verification Engineer in Hyderabad / Secunderabad

Full Time

Engineering - Hardware & Networks Department

4.0

• posted on 03 Jul 2023

4.0

for Salary and Benefits

Likes

I'm a trained Student at VLSI FIRST Institute in Hyderabad, This is completely front end developer- Hardware on RTL Design and Verification Engineer, the study of learning was very intresting and field was good and the projects are also good & the faculties are very good and a kind of friendly nature, You fully clarify the doughts finally this is good to work place and for the students also.

Salary - Good

+6 more

Dislikes

Nil!

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2w (edited)

an associate vice president

Offer Accepted

I was getting 15.2 LPA in my previous org and now i am being offered 29.5 LPA but the designation is 1 position lower than what i was in my previous org. Should i go ahead with the offer or still negotiate on designation. Protip : i was laid off in my previous org.

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VLSI FIRST Design & Verification Engineer Salary FAQs

What is the notice period for Design & Verification Engineer at VLSI FIRST in Bangalore / Bengaluru?

According to AmbitionBox, 50% of the VLSI FIRST Design & Verification Engineers in Bangalore / Bengaluru reported a notice period of 15 days or less, 50% reported a notice period of 3 Months.This is based on 2 responses on AmbitionBox in last 2 years.

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VLSI FIRST Design & Verification Engineer Salaries in Bangalore / Bengaluru

VLSI FIRST Design & Verification Engineer salary in Bangalore / Bengaluru ranges between ₹4.1 Lakhs to ₹5.2 Lakhs. This is an estimate based on latest salaries received from employees of VLSI FIRST.