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MasterVLSI Design and Verification Trainee salaries in India

Annual salary range
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₹6.3 Lakhs - ₹8 Lakhs
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Last Updated: 13 Oct 2024

Companies similar to MasterVLSI for Design and Verification Trainee

Company name Avg Annual Salary Open Jobs
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₹1 L/yr - ₹4 L/yr

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₹1.8 L/yr - ₹3.6 L/yr

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Design and Verification Trainee salary at MasterVLSI ranges between ₹6.3 Lakhs to ₹8 Lakhs per year for employees with 1 year of experience. Salary estimates are based on 1 latest salaries received from various employees of MasterVLSI.

Similar Designation salaries in MasterVLSI

Verification Engineer Salary
(AmbitionBox Estimate)
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₹1.8 L/yr - ₹2.3 L/yr

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MasterVLSI Design and Verification Trainee salary in India ranges between ₹6.3 Lakhs to ₹8 Lakhs. This is an estimate based on latest salaries received from employees of MasterVLSI.