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Premium Employer

Advanced Micro Devices

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3.8

based on 254 Reviews

Video summary

4 Advanced Micro Devices Verification Lead Jobs

IP/ Subsystem Verification Lead

Advanced Micro Devices, Inc

3.8

based on 254 Reviews

12-16 years

Bangalore / Bengaluru

1 vacancy

IP/ Subsystem Verification Lead

Advanced Micro Devices

posted 26d ago

Job Role Insights

Flexible timing

Key skills for the job

Electrical Engineering Recruitment Linux Administration Motion Graphics Ruby Rails Windows System Administration

+ 3 more

Job Description

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed and random verification tests
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues

Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements

PREFERRED EXPERIENCE:

Proficient in IP level ASIC verification
Proficient in debugging firmware and RTL code using simulation tools

Proficient in using UVM testbenches and working in Linux and Windows environment s
Experienced with Verilog, System Verilog, C, and C++
Graphics pipeline knowledge
Developing UVM based verification frameworks and testbenches, processes and flows
Automating workflows in a distributed compute environment .

Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
Strong background in the C++ language, preferably on Linux with exposure to Windows platform
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
Good working knowledge of SystemC and TLM with some related experience .
Scripting language experience: Perl, Ruby, Makefile , shell preferred.