PMTS Silicon Design Engineer

• Design and develop RTL code for DDR blocks in Verilog HDL and make sure they are functionally correct and reusable for different configurations based on architectural requirements.
• Conduct design reviews of designs in technical presentations to peers and management
• Oversees Synthesis and netlist delivery that meets timing, area and power bounding box. Assist physical design team on the floor-planning and timing closure.
• Work with Design Verification team to ensure quality for architecture definition and design implementation.

Requirement:

• MS or BS in Electrical Engineering/Computer Engineering/ Computer Science with 15+ years working experience in ASIC design industry.

• Knowledge in computer architecture and interconnects.
• Experience in high speed IO controller design (eg DDR, USB, PCIe, SATA, Ethernet). DDR experience is plus.
• Experience in full ASIC design cycle: Understanding spec requirement, RTL, design verification, floor-planning, synthesis, timing closure, power intent, post-silicon validation
• Expert on Verilog RTL design and has experience of large digital ASIC project.
• Familiar with front-end EDA tools and flows.
• Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc)
• Excellent interpersonal, communication, and writing skills. Able to provide clear and logical presentations and documentation. Has an open mind and attitude. Transparent. Willing to admit and learn from mistakes.
• Works well with others in a team environment
• Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as committed milestones.