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Vayavya Labs

Compare

3.8

based on 20 Reviews

4 Vayavya Labs Jobs

PSS Verification Lead

Vayavya Labs Pvt. Ltd

3.8

based on 20 Reviews

5-8 years

Bangalore / Bengaluru

1 vacancy

PSS Verification Lead

Vayavya Labs

posted 7d ago

Job Role Insights

Flexible timing

Key skills for the job

Hospital Social Work Risk Management FPGA Project Planning Debugging

+ 3 more

Job Description

PSS Verification Lead

Position: PSS Verification Lead

Experience: 5-8 Years

Location : Bengaluru, Karnataka

Job Description:

Understanding customer requirements on system-level verification scenarios
Development of test scenarios in PSS language and in C or SystemVerilog/UVM (as needed)
Execution of test scenarios in pre-silicon (simulation, emulation) and post-silicon environments
Debugging of the test scenarios

Job Brief:

Portable Stimulus (PSS) is a new industry standard that enables specification of test intent in a verification environment agnostic way. A test intent written in PSS can be used to generate verification scenarios for simulation, emulation, FPGA and post-silicon environments. PSS enables a significant productivity leap in chip/SoC Verification. Undoubtedly, PSS is the next big thing after SystemVerilog/UVM it carries forward tried and tested techniques from SystemVerilog (like Constraint Driven Verification and Coverage) to system level for pre/post-silicon verification.

Vayavya Labs has been one of the original contributors to this industry standard and actively driving the discussion for the last many years.

Many companies are adopting PSS to meet the challenges of verifying today s complex systems. Vayavya Labs is helping with this transition with years of expertise in Software-driven Verification and the PSS standard itself. See https: / / vayavyalabs.com / pss-hsi / for more information on the standard and what we as Vayavya Labs are contributing.

You will be part of the team working on Portable Stimulus technologies (PSS) and developing PSS-based scenarios for different SoC sub-systems PCIe, UCIe, CXL, GPU, MIPI CSI/DSI, and Ethernet to name a few. Other than functional verification, you will also work on system-level power verification, cache coherency, etc. Training on PSS will be provided as part of the ramp-up phase.

This is a great learning opportunity for an engineer with experience in developing system-level verification scenarios either in C or SystemVerilog/UVM. You get to work at the leading edge of SoC verification technologies.

Roles & Responsibilities:

Contributing to project planning, effort estimation and actively participating in timely deliverables and risk management keeping customer satisfaction in mind
Technical contribution towards identified tasks and modules
Technical leadership of a team or a module, managing dependencies
Mentoring/coaching other team members on PSS

Must-Have Technical Skills:

Hands-on experience in C programming as used in embedded systems (in bare-metal / RTOS or OS environments)
Experience in understanding datasheets and developing bare-metal APIs for pre-silicon validation
Expertise in Pre-Silicon validation of system-level scenarios in Simulation/Emulation Environments
Experienced with verification of controllers for one or more protocols like PCIe, CXL, Ethernet, MIPI CSI/DSI, USB, SPI, I2C, and GPIO.
Experienced in verification on emulator (Zebu/Palladium/Veloce) environments.

Good to Have Technical Skills:

Understanding complex I/O protocols like Ethernet, PCIe, USB, etc is a plus.
Expertise in Pre-Silicon validation of SoCs in Simulation/Emulation Environments
Exposure to power management of a modern SoC is a plus
Prior experience in PSS and Verification languages and methodologies (SystemVerilog/UVM) is a plus
Experience in directly working with customers